ASIC Design Engineer - Staff

Celero Communications, Inc. · Irvine, CA

Celero Communications, Inc.

11w ago

Irvine, CA

Full time

$150k – $250k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

+ 15

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System Verilog

HDL

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Sr. ASIC Design Verification Engineer (Starshield)

SpaceX

5w ago

Irvine, CA

Full time

$160k – $225k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Principal ASIC Design Verification Engineer (Starshield)

SpaceX

5w ago

Irvine, CA

Full time

$200k – $285k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

ASIC Design Engineer - Staff

Celero Communications, Inc.

11w ago

Irvine, CA

Full time

$150k – $250k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

+ 15

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

2w ago

Irvine, CA

Full time

$160k – $225k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Sr. ASIC Design Engineer (Starshield)

SpaceX

5w ago

Irvine, CA

Full time

$160k – $225k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Principal ASIC Design Engineer (Starshield)

SpaceX

5w ago

Irvine, CA

Full time

$200k – $285k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Design Verification Engineer (Silicon Engineering)

SpaceX

2w ago

Irvine, CA

Full time

$125k – $175k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

RTL Design Engineer (Silicon Engineering)

SpaceX

12w ago

Irvine, CA

Full time

$125k – $175k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

2w ago

Irvine, CA

Full time

$160k – $220k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX

2w ago

Irvine, CA

Full time

$165k – $230k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Principal Design Verification Engineer (Silicon Engineering)

SpaceX

2w ago

Irvine, CA

Full time

$210k – $300k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Sr. ASIC Design Verification Engineer (Starshield)

SpaceX

5w ago

Irvine, CA

Full time

$160k – $225k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

Principal ASIC Design Verification Engineer (Starshield)

SpaceX

5w ago

Irvine, CA

Full time

$200k – $285k

3+ years

Verilog

System Verilog

HDL

Synthesis

Timing Analysis

ASIC Design Engineer - Staff

at Celero Communications, Inc. | Full time

LocationIrvine, CA

Min Exp3+ years

Apply

About the role

About the Role:

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting-edge technologies.

Locations Available: Irvine, CA HQ, San Jose, CA, Austin, TX, Ottawa Ontario, CN, & Vancouver

Key Responsibilities:

Design and implement digital circuits using HDL (Verilog/ System Verilog).
Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis
Optimize designs for performance, power, and area (PPA) requirements.
Perform RTL simulation and verification to ensure design functionality.
Participate in design reviews and provide technical guidance to team members.
Collaborate with cross-functional teams on system integration and validation.

Qualifications:

Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field.
3+ years of experience in digital design and verification.
Proficiency in HDLs such as Verilog, or System Verilog.
Strong understanding of digital design principles and methodologies.
Familiarity with ASIC design flow, and experience with ASIC design tools.
Knowledge of low-power design techniques.
Familiarity with verification methodologies (e.g., UVM, formal verification).
Excellent problem-solving, strong communication and teamwork skills.

Preferred Skills

Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques.
Experience with scripting languages (e.g., Python, Tcl).
Understanding of Optical Communication Standards is a plus.
Ability to multitask and adapt to a fast-paced, dynamic environment.

Salary Range

$150,000 - $250,000 Base Annually
The final offer will be determined based on job-related skills, experience, qualifications, and location.

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